155 lines
8.0 KiB
C
155 lines
8.0 KiB
C
/*
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*********************************************************************************************************
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* EXAMPLE CODE
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*
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* This file is provided as an example on how to use Micrium products.
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*
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* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
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* your application products. Example code may be used as is, in whole or in
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* part, or may be used as a reference only. This file can be modified as
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* required to meet the end-product requirements.
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*
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* Please help us continue to provide the Embedded community with the finest
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* software available. Your honesty is greatly appreciated.
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*
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* You can find our product's user manual, API reference, release notes and
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* more information at https://doc.micrium.com.
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* You can contact us at www.micrium.com.
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* BOARD SUPPORT PACKAGE
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*
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* Texas Instruments TM4C129x
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* on the
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*
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* DK-TM4C129X
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* Development Kit
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*
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* Filename : bsp_sys.h
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* Version : V1.00
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* Programmer(s) : FF
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*********************************************************************************************************
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*/
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#include <cpu.h>
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/*
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*********************************************************************************************************
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* DEFINES
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*********************************************************************************************************
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*/
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#define BSP_CFG_PLL_N 4u
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#define BSP_CFG_PLL_Q 0u
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#define BSP_CFG_PLL_MINT 96u
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#define BSP_CFG_PLL_MFRAC 0u
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#define BSP_CFG_PLL_SYS_PSYSDIV 3u
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/*
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*********************************************************************************************************
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* REGISTERS
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*********************************************************************************************************
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*/
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#define BSP_SYS_BASE_ADDR 0x400FE000u
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#define BSP_SYS_REG_MOSCCTL (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x007Cu))
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#define BSP_SYS_REG_RSCLKCFG (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x00B0u))
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#define BSP_SYS_REG_MEMTIM0 (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x00C0u))
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#define BSP_SYS_REG_PLLFREQ0 (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x0160u))
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#define BSP_SYS_REG_PLLFREQ1 (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x0164u))
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#define BSP_SYS_REG_PLLSTAT (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x0168u))
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#define BSP_SYS_REG_RCGCGPIO (*(CPU_REG32 *)(BSP_SYS_BASE_ADDR + 0x0608u))
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/*
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*********************************************************************************************************
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* REGISTER BITS
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*********************************************************************************************************
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*/
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#define BSP_MOSCCTL_SESRC DEF_BIT_05
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#define BSP_MOSCCTL_OSCRNG DEF_BIT_04
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#define BSP_MOSCCTL_PWRDN DEF_BIT_03
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#define BSP_MOSCCTL_NOXTAL DEF_BIT_02
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#define BSP_MOSCCTL_MOSCIM DEF_BIT_01
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#define BSP_MOSCCTL_CVAL DEF_BIT_00
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#define BSP_RSCLKCFG_MEMTIMU DEF_BIT_31
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#define BSP_RSCLKCFG_NEWFREQ DEF_BIT_30
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#define BSP_RSCLKCFG_ACG DEF_BIT_29
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#define BSP_RSCLKCFG_USEPLL DEF_BIT_28
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#define BSP_RSCLKCFG_PLLSRC_PIOSC DEF_BIT_NONE
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#define BSP_RSCLKCFG_PLLSRC_MOSC DEF_BIT_MASK(3u, 24u)
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#define BSP_RSCLKCFG_OSCSRC_PIOSC DEF_BIT_NONE
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#define BSP_RSCLKCFG_OSCSRC_LFIOSC DEF_BIT_MASK(2u, 20u)
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#define BSP_RSCLKCFG_OSCSRC_MOSC DEF_BIT_MASK(3u, 20u)
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#define BSP_RSCLKCFG_OSCSRC_RTCOSC DEF_BIT_MASK(4u, 20u)
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#define BSP_RSCLKCFG_OSYSDIV_MASK DEF_BIT_FIELD(10u, 10u)
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#define BSP_RSCLKCFG_PSYSDIV_MASK DEF_BIT_FIELD(10u, 0u)
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#define BSP_MEMTIM0_EBCE DEF_BIT_21
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#define BSP_MEMTIM0_FBCE DEF_BIT_05
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#define BSP_MEMTIM0_xBCHT_SYS_CLK_HIGH 0u
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#define BSP_MEMTIM0_xBCHT_1 1u
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#define BSP_MEMTIM0_xBCHT_1_5 2u
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#define BSP_MEMTIM0_xBCHT_2 3u
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#define BSP_MEMTIM0_xBCHT_2_5 4u
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#define BSP_MEMTIM0_xBCHT_3 5u
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#define BSP_MEMTIM0_xBCHT_3_5 6u
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#define BSP_MEMTIM0_xBCHT_4 7u
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#define BSP_MEMTIM0_xBCHT_4_5 8u
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#define BSP_MEMTIM0_EBCHT_MASK DEF_BIT_FIELD(4u, 22u)
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#define BSP_MEMTIM0_FBCHT_MASK DEF_BIT_FIELD(4u, 6u)
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#define BSP_MEMTIM0_WS_0 0u
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#define BSP_MEMTIM0_WS_1 1u
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#define BSP_MEMTIM0_WS_2 2u
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#define BSP_MEMTIM0_WS_3 3u
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#define BSP_MEMTIM0_WS_4 4u
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#define BSP_MEMTIM0_WS_5 5u
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#define BSP_MEMTIM0_WS_6 6u
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#define BSP_MEMTIM0_WS_7 7u
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#define BSP_MEMTIM0_EWS_MASK DEF_BIT_FIELD(4u, 16u)
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#define BSP_MEMTIM0_FWS_MASK DEF_BIT_FIELD(4u, 0u)
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#define BSP_PLLFREQ0_PLLPWR DEF_BIT_23
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#define BSP_PLLFREQ0_MFRAC_MASK DEF_BIT_FIELD(10u, 10u)
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#define BSP_PLLFREQ0_MINT_MASK DEF_BIT_FIELD(10u, 0u)
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#define BSP_PLLFREQ1_Q_MASK DEF_BIT_FIELD(5u, 8u)
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#define BSP_PLLFREQ1_N_MASK DEF_BIT_FIELD(5u, 0u)
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#define BSP_PLLSTAT_LOCK DEF_BIT_00
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#define BSP_RCGCGPIO_PORT_T DEF_BIT_17
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#define BSP_RCGCGPIO_PORT_S DEF_BIT_16
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#define BSP_RCGCGPIO_PORT_R DEF_BIT_15
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#define BSP_RCGCGPIO_PORT_Q DEF_BIT_14
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#define BSP_RCGCGPIO_PORT_P DEF_BIT_13
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#define BSP_RCGCGPIO_PORT_N DEF_BIT_12
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#define BSP_RCGCGPIO_PORT_M DEF_BIT_11
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#define BSP_RCGCGPIO_PORT_L DEF_BIT_10
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#define BSP_RCGCGPIO_PORT_K DEF_BIT_09
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#define BSP_RCGCGPIO_PORT_J DEF_BIT_08
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#define BSP_RCGCGPIO_PORT_H DEF_BIT_07
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#define BSP_RCGCGPIO_PORT_G DEF_BIT_06
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#define BSP_RCGCGPIO_PORT_F DEF_BIT_05
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#define BSP_RCGCGPIO_PORT_E DEF_BIT_04
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#define BSP_RCGCGPIO_PORT_D DEF_BIT_03
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#define BSP_RCGCGPIO_PORT_C DEF_BIT_02
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#define BSP_RCGCGPIO_PORT_B DEF_BIT_01
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#define BSP_RCGCGPIO_PORT_A DEF_BIT_00
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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void BSP_SysInit (void);
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CPU_INT32U BSP_SysClkFreqGet(void);
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