215 lines
10 KiB
C
215 lines
10 KiB
C
/*
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*********************************************************************************************************
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* EXAMPLE CODE
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*
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* This file is provided as an example on how to use Micrium products.
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*
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* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
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* your application products. Example code may be used as is, in whole or in
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* part, or may be used as a reference only. This file can be modified as
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* required to meet the end-product requirements.
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*
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* Please help us continue to provide the Embedded community with the finest
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* software available. Your honesty is greatly appreciated.
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*
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* You can find our product's user manual, API reference, release notes and
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* more information at https://doc.micrium.com.
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* You can contact us at www.micrium.com.
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* BOARD SUPPORT PACKAGE
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*
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* Texas Instruments TM4C129x
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* on the
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*
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* DK-TM4C129X
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* Development Kit
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*
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* Filename : bsp_sys.c
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* Version : V1.00
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* Programmer(s) : FF
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* INCLUDES
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*********************************************************************************************************
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*/
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#include <bsp_cfg.h>
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#include <lib_def.h>
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#include <bsp_sys.h>
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* BSP SYSTEM INITIALIZATION
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*
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* Description: This function should be called early in the BSP initialization process.
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*
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* Argument(s): none.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : 1) Ensure the main oscillator is enable because this is required by the PHY. The system
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* must have a 25MHz crystal attached to the OSC pins. The SYSCTL_MOS_HIGHFREQ parameter
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* is used when the crystal frequency is 10MHz or higher.
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*
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* 2) Depending on the CPU frequency, the application must program the Main Flash and EEPROM
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* memory timing paremeters according to the following table:
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*
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* +-----------------------+--------------------------+-------------+-----------+---------+
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* | CPU Freq. Range(F) in | Time Period Range (t) in | FBCHT/EBCHT | FBCE/EBCE | FWS/EWS |
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* | MHz | ns | | | |
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* +-----------------------+--------------------------+-------------+-----------+---------+
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* | 16 | 62.5 | 0x0 | 1 | 0x0 |
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* | 16 < f <= 40 | 62.5 > f >= 25 | 0x2 | 0 | 0x1 |
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* | 40 < f <= 60 | 25 > f >= 16.67 | 0x3 | 0 | 0x2 |
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* | 60 < f <= 80 | 16.67 > f >= 12.5 | 0x4 | 0 | 0x3 |
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* | 80 < f <= 100 | 12.5 > f >= 10 | 0x5 | 0 | 0x4 |
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* | 100 < f <= 120 | 10 > f >= 8.33 | 0x6 | 0 | 0x5 |
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* +-----------------------+--------------------------+-------------+-----------+---------+
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*********************************************************************************************************
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*/
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void BSP_SysInit (void)
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{
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/* Enable xtal crystal oscillator */
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DEF_BIT_CLR(BSP_SYS_REG_MOSCCTL, (BSP_MOSCCTL_OSCRNG |
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BSP_MOSCCTL_NOXTAL |
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BSP_MOSCCTL_PWRDN));
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DEF_BIT_SET(BSP_SYS_REG_MOSCCTL, BSP_MOSCCTL_OSCRNG); /* See Note 1. */
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/* Set Flash & EEPROM timing CPU freq = 25Mhz */
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/* See Note 2. */
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DEF_BIT_CLR(BSP_SYS_REG_MEMTIM0, (BSP_MEMTIM0_EBCHT_MASK |
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BSP_MEMTIM0_FBCHT_MASK |
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BSP_MEMTIM0_EWS_MASK |
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BSP_MEMTIM0_FWS_MASK |
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BSP_MEMTIM0_EBCE |
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BSP_MEMTIM0_FBCE));
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BSP_SYS_REG_MEMTIM0 |= ((BSP_MEMTIM0_WS_1 << 0) | /* Set FWS */
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(BSP_MEMTIM0_WS_1 << 16) | /* Set EWS */
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(BSP_MEMTIM0_xBCHT_1_5 << 6));
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/* ---------------- PLL CONFIGURATION ----------------- */
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/* Update memory timing to match running from PIOSC .. */
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BSP_SYS_REG_RSCLKCFG = BSP_RSCLKCFG_MEMTIMU; /* .. and clear old PLL divider and source */
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BSP_SYS_REG_RSCLKCFG = (BSP_RSCLKCFG_OSCSRC_MOSC | /* Select MOSC = 25Mhz for PLL input clk & Osc source */
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BSP_RSCLKCFG_PLLSRC_MOSC);
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/* MDIV = MINT + (MFRAC / 1024) */
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/* MDIV = 96 + (0 / 1024) = 96 */
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BSP_SYS_REG_PLLFREQ0 = ((BSP_CFG_PLL_MFRAC << 10u) |
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(BSP_CFG_PLL_MINT << 0u));
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/* Fvco freq = (fmosc * MDIV) / ((Q + 1) * (N + 1)) */
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/* = (25MHz * 96) / (0 + 1) * (4 + 1)) */
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/* = 480MHz */
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BSP_SYS_REG_PLLFREQ1 = ((BSP_CFG_PLL_Q << 8u) |
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(BSP_CFG_PLL_N << 0u));
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/* Prepare Flash & EEPROM timing for CPU freq = 120Mhz */
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/* See Note 2. */
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DEF_BIT_CLR(BSP_SYS_REG_MEMTIM0, (BSP_MEMTIM0_EBCHT_MASK |
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BSP_MEMTIM0_FBCHT_MASK |
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BSP_MEMTIM0_EWS_MASK |
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BSP_MEMTIM0_FWS_MASK |
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BSP_MEMTIM0_EBCE |
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BSP_MEMTIM0_FBCE));
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BSP_SYS_REG_MEMTIM0 |= ((BSP_MEMTIM0_xBCHT_3_5 << 22u) |
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(BSP_MEMTIM0_WS_5 << 16u) |
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(BSP_MEMTIM0_xBCHT_3_5 << 6u) |
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(BSP_MEMTIM0_WS_5 << 0u));
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DEF_BIT_SET(BSP_SYS_REG_PLLFREQ0, BSP_PLLFREQ0_PLLPWR); /* PLL power is applied. */
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/* Wait for PLL to power and lock. */
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while (DEF_BIT_IS_CLR(BSP_SYS_REG_PLLSTAT, BSP_PLLSTAT_LOCK) == DEF_YES) {
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;
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}
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/* SysClk = Fvco / (PSYSDIV + 1 ) */
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/* = 480MHz / (3 + 1) = 120MHz */
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BSP_SYS_REG_RSCLKCFG |= ((BSP_CFG_PLL_SYS_PSYSDIV) |
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BSP_RSCLKCFG_USEPLL |
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BSP_RSCLKCFG_MEMTIMU); /* Update memory timing to match running from Sysclk */
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}
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/*
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*********************************************************************************************************
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* SYSTEM CLOCK FREQUENCY
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*
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* Description: This function is used to retrieve system or CPU clock frequency.
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*
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* Arguments : None
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*
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* Return : System clock frequency in cycles.
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*
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* Caller(s) : Application.
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*
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* Note(s) : None
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*********************************************************************************************************
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*/
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CPU_INT32U BSP_SysClkFreqGet (void)
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{
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CPU_INT32U pll_mdiv;
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CPU_INT16U pll_mint;
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CPU_INT16U pll_mfrac;
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CPU_INT16U pll_q;
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CPU_INT16U pll_n;
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CPU_INT32U sys_div;
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CPU_INT32U sys_freq;
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CPU_INT32U pll_src;
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if ((DEF_BIT_IS_SET(BSP_SYS_REG_RSCLKCFG, BSP_RSCLKCFG_USEPLL)) == DEF_YES) {
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pll_mfrac = (BSP_SYS_REG_PLLFREQ0 >> 10u) & 0x07FFu;
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pll_mint = (BSP_SYS_REG_PLLFREQ0 ) & 0x07FFu;
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pll_mdiv = (pll_mint + (pll_mfrac / 1024u));
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pll_q = (BSP_SYS_REG_PLLFREQ1 >> 8) & 0x1Fu;
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pll_n = (BSP_SYS_REG_PLLFREQ1 ) & 0x1Fu;
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pll_src = (BSP_SYS_REG_RSCLKCFG >> 24u) & 0x0Fu;
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switch (pll_src) {
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case 0:
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pll_src = BSP_CFG_SYS_INT_CLK_FREQ;
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break;
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case 3:
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pll_src = BSP_CFG_SYS_EXT_CLK_FREQ;
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break;
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default:
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break;
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}
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sys_freq = ((pll_src * pll_mdiv) / ((pll_q + 1u) * (pll_n + 1u)));
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sys_div = (BSP_SYS_REG_RSCLKCFG & BSP_RSCLKCFG_PSYSDIV_MASK) + 1u;
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sys_freq = sys_freq / sys_div;
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} else {
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sys_freq = 0u;
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}
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return (sys_freq);
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}
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