ARM Macro Assembler Page 1 1 00000000 ; 2 00000000 ;******************************************************* ************************************************* 3 00000000 ; uC/OS-I I 4 00000000 ; The Real-Time Kernel 5 00000000 ; 6 00000000 ; 7 00000000 ; (c) Copyright 2009-2013; Micri um, Inc.; Weston, FL 8 00000000 ; All rights reserved. Protected by international copyright laws. 9 00000000 ; 10 00000000 ; ARM Cortex-M 4 Port 11 00000000 ; 12 00000000 ; File : OS_CPU_A.ASM 13 00000000 ; Version : V2.92.09 14 00000000 ; By : JJL 15 00000000 ; BAN 16 00000000 ; JBL 17 00000000 ; 18 00000000 ; For : ARMv7 Cortex-M4 19 00000000 ; Mode : Thumb-2 ISA 20 00000000 ; Toolchain : RealView Development Suite 21 00000000 ; RealView Microcontroller Development Kit ( MDK) 22 00000000 ; ARM Developer Suite (ADS) 23 00000000 ; Keil uVision 24 00000000 ;******************************************************* ************************************************* 25 00000000 ; 26 00000000 27 00000000 ;******************************************************* ************************************************* 28 00000000 ; PUBLIC FUNCTI ONS 29 00000000 ;******************************************************* ************************************************* 30 00000000 31 00000000 EXTERN OSRunning ; External referenc es 32 00000000 EXTERN OSPrioCur 33 00000000 EXTERN OSPrioHighRdy 34 00000000 EXTERN OSTCBCur 35 00000000 EXTERN OSTCBHighRdy 36 00000000 EXTERN OSIntExit 37 00000000 EXTERN OSTaskSwHook 38 00000000 EXTERN OS_CPU_ExceptStkBase 39 00000000 40 00000000 EXPORT OS_CPU_SR_Save ; Functions decl ared in this file 41 00000000 EXPORT OS_CPU_SR_Restore 42 00000000 EXPORT OSStartHighRdy 43 00000000 EXPORT OSCtxSw 44 00000000 EXPORT OSIntCtxSw 45 00000000 EXPORT OS_CPU_PendSVHandler 46 00000000 ARM Macro Assembler Page 2 47 00000000 IF {FPU} != "SoftVFP" 48 00000000 EXPORT OS_CPU_FP_Reg_Push 49 00000000 EXPORT OS_CPU_FP_Reg_Pop 50 00000000 ENDIF 51 00000000 52 00000000 53 00000000 ;******************************************************* ************************************************* 54 00000000 ; EQUATES 55 00000000 ;******************************************************* ************************************************* 56 00000000 57 00000000 E000ED04 NVIC_INT_CTRL EQU 0xE000ED04 ; Interrupt control state register. 58 00000000 E000ED22 NVIC_SYSPRI14 EQU 0xE000ED22 ; System priority r egister (priority 1 4). 59 00000000 000000FF NVIC_PENDSV_PRI EQU 0xFF ; PendSV priority v alue (lowest). 60 00000000 10000000 NVIC_PENDSVSET EQU 0x10000000 ; Value to trigger PendSV exception. 61 00000000 62 00000000 63 00000000 ;******************************************************* ************************************************* 64 00000000 ; CODE GENERATION DI RECTIVES 65 00000000 ;******************************************************* ************************************************* 66 00000000 67 00000000 AREA |.text|, CODE, READONLY, ALIGN= 2 68 00000000 THUMB 69 00000000 REQUIRE8 70 00000000 PRESERVE8 71 00000000 72 00000000 73 00000000 ;******************************************************* ************************************************* 74 00000000 ; FLOATING POINT REGIS TERS PUSH 75 00000000 ; void OS_CPU_FP_Reg_Push ( CPU_STK *stkPtr) 76 00000000 ; 77 00000000 ; Note(s) : 1) This function saves S0-S31, and FPSCR reg isters of the Floating Point Unit. 78 00000000 ; 79 00000000 ; 2) Pseudo-code is: 80 00000000 ; a) Get FPSCR register value; 81 00000000 ; b) Push value on process stack; 82 00000000 ; c) Push remaining regs S0-S31 on process ARM Macro Assembler Page 3 stack; 83 00000000 ; d) Update OSTCBCurPtr->StkPtr; 84 00000000 ;******************************************************* ************************************************* 85 00000000 86 00000000 IF {FPU} != "SoftVFP" 87 00000000 88 00000000 OS_CPU_FP_Reg_Push 89 00000000 F3EF 8109 MRS R1, PSP ; PSP is process st ack pointer 90 00000004 B141 CBZ R1, OS_CPU_FP_nosave ; Skip FP register save the f irst time 91 00000006 92 00000006 EEF1 1A10 VMRS R1, FPSCR 93 0000000A F840 1D04 STR R1, [R0, #-4]! 94 0000000E ED20 0A20 VSTMDB R0!, {S0-S31} 95 00000012 4929 LDR R1, =OSTCBCur 96 00000014 680A LDR R2, [R1] 97 00000016 6010 STR R0, [R2] 98 00000018 OS_CPU_FP_nosave 99 00000018 4770 BX LR 100 0000001A 101 0000001A ENDIF 102 0000001A 103 0000001A 104 0000001A ;******************************************************* ************************************************* 105 0000001A ; FLOATING POINT REGIS TERS POP 106 0000001A ; void OS_CPU_FP_Reg_Pop (C PU_STK *stkPtr) 107 0000001A ; 108 0000001A ; Note(s) : 1) This function restores S0-S31, and FPSCR registers of the Floating Point Unit. 109 0000001A ; 110 0000001A ; 2) Pseudo-code is: 111 0000001A ; a) Restore regs S0-S31 of new process sta ck; 112 0000001A ; b) Restore FPSCR reg value 113 0000001A ; c) Update OSTCBHighRdyPtr->StkPtr pointer of new proces stack; 114 0000001A ;******************************************************* ************************************************* 115 0000001A 116 0000001A IF {FPU} != "SoftVFP" 117 0000001A 118 0000001A OS_CPU_FP_Reg_Pop 119 0000001A ECB0 0A20 VLDMIA R0!, {S0-S31} 120 0000001E C802 LDMIA R0!, {R1} 121 00000020 EEE1 1A10 VMSR FPSCR, R1 122 00000024 4925 LDR R1, =OSTCBHighRdy 123 00000026 680A LDR R2, [R1] 124 00000028 6010 STR R0, [R2] 125 0000002A 4770 BX LR 126 0000002C 127 0000002C ENDIF 128 0000002C 129 0000002C ARM Macro Assembler Page 4 130 0000002C ;******************************************************* ************************************************* 131 0000002C ; CRITICAL SECTION MET HOD 3 FUNCTIONS 132 0000002C ; 133 0000002C ; Description: Disable/Enable interrupts by preserving t he state of interrupts. Generally speaking you 134 0000002C ; would store the state of the interrupt di sable flag in the local variable 'cpu_sr' and then 135 0000002C ; disable interrupts. 'cpu_sr' is allocate d in all of uC/OS-II's functions that need to 136 0000002C ; disable interrupts. You would restore th e interrupt disable state by copying back 'cpu_sr' 137 0000002C ; into the CPU's status register. 138 0000002C ; 139 0000002C ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void); 140 0000002C ; void OS_CPU_SR_Restore(OS_CPU_S R cpu_sr); 141 0000002C ; 142 0000002C ; 143 0000002C ; Note(s) : 1) These functions are used in general li ke this: 144 0000002C ; 145 0000002C ; void Task (void *p_arg) 146 0000002C ; { 147 0000002C ; #if OS_CRITICAL_METHOD == 3 / * Allocate storage for CPU status register */ 148 0000002C ; OS_CPU_SR cpu_sr; 149 0000002C ; #endif 150 0000002C ; 151 0000002C ; : 152 0000002C ; : 153 0000002C ; OS_ENTER_CRITICAL(); / * cpu_sr = OS_CPU_SaveSR(); */ 154 0000002C ; : 155 0000002C ; : 156 0000002C ; OS_EXIT_CRITICAL(); / * OS_CPU_RestoreSR(cpu_sr); */ 157 0000002C ; : 158 0000002C ; : 159 0000002C ; } 160 0000002C ;******************************************************* ************************************************* 161 0000002C 162 0000002C OS_CPU_SR_Save 163 0000002C F3EF 8010 MRS R0, PRIMASK ; Set prio int mask to mask all (excep t faults) 164 00000030 B672 CPSID I 165 00000032 4770 BX LR 166 00000034 167 00000034 OS_CPU_SR_Restore 168 00000034 F380 8810 MSR PRIMASK, R0 169 00000038 4770 BX LR 170 0000003A 171 0000003A 172 0000003A ;******************************************************* ************************************************* 173 0000003A ; START MULTITAS ARM Macro Assembler Page 5 KING 174 0000003A ; void OSStartHighR dy(void) 175 0000003A ; 176 0000003A ; Note(s) : 1) This function triggers a PendSV exception (essentially, causes a context switch) to cause 177 0000003A ; the first task to start. 178 0000003A ; 179 0000003A ; 2) OSStartHighRdy() MUST: 180 0000003A ; a) Setup PendSV exception priority to low est; 181 0000003A ; b) Set initial PSP to 0, to tell context switcher this is first run; 182 0000003A ; c) Set the main stack to OS_CPU_ExceptStk Base 183 0000003A ; d) Set OSRunning to TRUE; 184 0000003A ; e) Trigger PendSV exception; 185 0000003A ; f) Enable interrupts (tasks will run with interrupts enabled). 186 0000003A ;******************************************************* ************************************************* 187 0000003A 188 0000003A OSStartHighRdy 189 0000003A 4821 LDR R0, =NVIC_SYSPRI14 ; Set the Pe ndSV exception prio rity 190 0000003C F04F 01FF LDR R1, =NVIC_PENDSV_PRI 191 00000040 7001 STRB R1, [R0] 192 00000042 193 00000042 2000 MOVS R0, #0 ; Set the PSP to 0 for initial context switch call 194 00000044 F380 8809 MSR PSP, R0 195 00000048 196 00000048 481E LDR R0, =OS_CPU_ExceptStkBase ; Ini tialize the MSP to the OS_CPU_ExceptSt kBase 197 0000004A 6801 LDR R1, [R0] 198 0000004C F381 8808 MSR MSP, R1 199 00000050 200 00000050 481D LDR R0, =OSRunning ; OSRunning = TRUE 201 00000052 2101 MOVS R1, #1 202 00000054 7001 STRB R1, [R0] 203 00000056 204 00000056 481D LDR R0, =NVIC_INT_CTRL ; Trigger th e PendSV exception (causes context swi tch) 205 00000058 F04F 5180 LDR R1, =NVIC_PENDSVSET 206 0000005C 6001 STR R1, [R0] 207 0000005E 208 0000005E B662 CPSIE I ; Enable interrupts at processor level 209 00000060 210 00000060 OSStartHang 211 00000060 E7FE B OSStartHang ; Should never get ARM Macro Assembler Page 6 here 212 00000062 213 00000062 214 00000062 ;******************************************************* ************************************************* 215 00000062 ; PERFORM A CONTEXT SWITCH (From t ask level) - OSCtxSw() 216 00000062 ; 217 00000062 ; Note(s) : 1) OSCtxSw() is called when OS wants to perf orm a task context switch. This function 218 00000062 ; triggers the PendSV exception which is wh ere the real work is done. 219 00000062 ;******************************************************* ************************************************* 220 00000062 221 00000062 OSCtxSw 222 00000062 481A LDR R0, =NVIC_INT_CTRL ; Trigger th e PendSV exception (causes context swi tch) 223 00000064 F04F 5180 LDR R1, =NVIC_PENDSVSET 224 00000068 6001 STR R1, [R0] 225 0000006A 4770 BX LR 226 0000006C 227 0000006C 228 0000006C ;******************************************************* ************************************************* 229 0000006C ; PERFORM A CONTEXT SWITCH (From inter rupt level) - OSIntCtxSw() 230 0000006C ; 231 0000006C ; Note(s) : 1) OSIntCtxSw() is called by OSIntExit() whe n it determines a context switch is needed as 232 0000006C ; the result of an interrupt. This functio n simply triggers a PendSV exception which will 233 0000006C ; be handled when there are no more interru pts active and interrupts are enabled. 234 0000006C ;******************************************************* ************************************************* 235 0000006C 236 0000006C OSIntCtxSw 237 0000006C 4817 LDR R0, =NVIC_INT_CTRL ; Trigger th e PendSV exception (causes context swi tch) 238 0000006E F04F 5180 LDR R1, =NVIC_PENDSVSET 239 00000072 6001 STR R1, [R0] 240 00000074 4770 BX LR 241 00000076 242 00000076 243 00000076 ;******************************************************* ************************************************* 244 00000076 ; HANDLE PendSV EX CEPTION 245 00000076 ; void OS_CPU_PendSVHa ndler(void) 246 00000076 ; 247 00000076 ; Note(s) : 1) PendSV is used to cause a context switch. This is a recommended method for performing 248 00000076 ; context switches with Cortex-M3. This is ARM Macro Assembler Page 7 because the Cortex-M3 auto-saves half of the 249 00000076 ; processor context on any exception, and r estores same on return from exception. So only 250 00000076 ; saving of R4-R11 is required and fixing u p the stack pointers. Using the PendSV exception 251 00000076 ; this way means that context saving and re storing is identical whether it is initiated from 252 00000076 ; a thread or occurs due to an interrupt or exception. 253 00000076 ; 254 00000076 ; 2) Pseudo-code is: 255 00000076 ; a) Get the process SP, if 0 then skip (go to d) the saving part (first context switch); 256 00000076 ; b) Save remaining regs r4-r11 on process stack; 257 00000076 ; c) Save the process SP in its TCB, OSTCBC ur->OSTCBStkPtr = SP; 258 00000076 ; d) Call OSTaskSwHook(); 259 00000076 ; e) Get current high priority, OSPrioCur = OSPrioHighRdy; 260 00000076 ; f) Get current ready thread TCB, OSTCBCur = OSTCBHighRdy; 261 00000076 ; g) Get new process SP from TCB, SP = OSTC BHighRdy->OSTCBStkPtr; 262 00000076 ; h) Restore R4-R11 from new process stack; 263 00000076 ; i) Perform exception return which will re store remaining context. 264 00000076 ; 265 00000076 ; 3) On entry into PendSV handler: 266 00000076 ; a) The following have been saved on the p rocess stack (by processor): 267 00000076 ; xPSR, PC, LR, R12, R0-R3 268 00000076 ; b) Processor mode is switched to Handler mode (from Thread mode) 269 00000076 ; c) Stack is Main stack (switched from Pro cess stack) 270 00000076 ; d) OSTCBCur points to the OS_TCB of the task to suspend 271 00000076 ; OSTCBHighRdy points to the OS_TCB of the task to resume 272 00000076 ; 273 00000076 ; 4) Since PendSV is set to lowest priority in the system (by OSStartHighRdy() above), we 274 00000076 ; know that it will only be run when no oth er exception or interrupt is active, and 275 00000076 ; therefore safe to assume that context bei ng switched out was using the process stack (PSP). 276 00000076 ;******************************************************* ************************************************* 277 00000076 278 00000076 OS_CPU_PendSVHandler 279 00000076 B672 CPSID I ; Prevent interrupt ion during context switch 280 00000078 F3EF 8009 MRS R0, PSP ; PSP is process st ack pointer 281 0000007C B128 CBZ R0, OS_CPU_PendSVHandler_nosave ARM Macro Assembler Page 8 ; Skip register sav e the first time 282 0000007E 283 0000007E 3820 SUBS R0, R0, #0x20 ; Save remaining regs r4-11 on proce ss stack 284 00000080 E880 0FF0 STM R0, {R4-R11} 285 00000084 286 00000084 490C LDR R1, =OSTCBCur ; OSTCBCur->OSTCB StkPtr = SP; 287 00000086 6809 LDR R1, [R1] 288 00000088 6008 STR R0, [R1] ; R0 is SP of proce ss being switched o ut 289 0000008A 290 0000008A ; At this point, entire context of process has been save d 291 0000008A OS_CPU_PendSVHandler_nosave 292 0000008A B500 PUSH {R14} ; Save LR exc_retur n value 293 0000008C 4810 LDR R0, =OSTaskSwHook ; OSTaskSwHook(); 294 0000008E 4780 BLX R0 295 00000090 F85D EB04 POP {R14} 296 00000094 297 00000094 480F LDR R0, =OSPrioCur ; OSPrioCur = OS PrioHighRdy; 298 00000096 4910 LDR R1, =OSPrioHighRdy 299 00000098 780A LDRB R2, [R1] 300 0000009A 7002 STRB R2, [R0] 301 0000009C 302 0000009C 4806 LDR R0, =OSTCBCur ; OSTCBCur = OST CBHighRdy; 303 0000009E 4907 LDR R1, =OSTCBHighRdy 304 000000A0 680A LDR R2, [R1] 305 000000A2 6002 STR R2, [R0] 306 000000A4 307 000000A4 6810 LDR R0, [R2] ; R0 is new process SP; SP = OSTCBHigh Rdy->OSTCBStkPtr; 308 000000A6 E890 0FF0 LDM R0, {R4-R11} ; Restore r4-11 fr om new process stac k 309 000000AA 3020 ADDS R0, R0, #0x20 310 000000AC F380 8809 MSR PSP, R0 ; Load PSP with new process SP 311 000000B0 F04E 0EF4 ORR LR, LR, #0xF4 ; Ensure exceptio n return uses proce ss stack 312 000000B4 B662 CPSIE I 313 000000B6 4770 BX LR ; Exception return will restore remain ing context 314 000000B8 315 000000B8 END 00000000 00000000 E000ED22 00000000 ARM Macro Assembler Page 9 00000000 E000ED04 00000000 00000000 00000000 Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp --apcs=int erwork --depend=.\objects\os_cpu_a.d -o.\objects\os_cpu_a.o -ID:\Project\Åàѵ\R TCGet(3)\Project\MDK\RTE -I"D:\Program Files\Keil_v5\ARM\PACK\Keil\TM4C_DFP\1.1 .0\Device\Include\TM4C129" -I"D:\Program Files\Keil_v5\ARM\CMSIS\Include" --pre define="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 518" --predefine ="TM4C1292NCPDT SETA 1" --list=.\listings\os_cpu_a.lst ..\..\Src\Micrium-DK-TM4 C129X-OS2\uCOS-II\Ports\ARM-Cortex-M4\Generic\RealView\os_cpu_a.asm ARM Macro Assembler Page 1 Alphabetic symbol ordering Relocatable symbols .text 00000000 Symbol: .text Definitions At line 67 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses None Comment: .text unused OSCtxSw 00000062 Symbol: OSCtxSw Definitions At line 221 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 43 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OSCtxSw used once OSIntCtxSw 0000006C Symbol: OSIntCtxSw Definitions At line 236 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 44 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OSIntCtxSw used once OSStartHang 00000060 Symbol: OSStartHang Definitions At line 210 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 211 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OSStartHang used once OSStartHighRdy 0000003A Symbol: OSStartHighRdy Definitions At line 188 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 42 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OSStartHighRdy used once OS_CPU_FP_Reg_Pop 0000001A Symbol: OS_CPU_FP_Reg_Pop Definitions At line 118 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 49 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_FP_Reg_Pop used once ARM Macro Assembler Page 2 Alphabetic symbol ordering Relocatable symbols OS_CPU_FP_Reg_Push 00000000 Symbol: OS_CPU_FP_Reg_Push Definitions At line 88 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 48 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_FP_Reg_Push used once OS_CPU_FP_nosave 00000018 Symbol: OS_CPU_FP_nosave Definitions At line 98 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 90 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_FP_nosave used once OS_CPU_PendSVHandler 00000076 Symbol: OS_CPU_PendSVHandler Definitions At line 278 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 45 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_PendSVHandler used once OS_CPU_PendSVHandler_nosave 0000008A Symbol: OS_CPU_PendSVHandler_nosave Definitions At line 291 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 281 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_PendSVHandler_nosave used once OS_CPU_SR_Restore 00000034 Symbol: OS_CPU_SR_Restore Definitions At line 167 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 41 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_SR_Restore used once OS_CPU_SR_Save 0000002C Symbol: OS_CPU_SR_Save Definitions At line 162 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Uses At line 40 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm ARM Macro Assembler Page 3 Alphabetic symbol ordering Relocatable symbols Comment: OS_CPU_SR_Save used once 12 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering Absolute symbols NVIC_INT_CTRL E000ED04 Symbol: NVIC_INT_CTRL Definitions At line 57 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 204 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 222 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 237 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm NVIC_PENDSVSET 10000000 Symbol: NVIC_PENDSVSET Definitions At line 60 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 205 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 223 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 238 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm NVIC_PENDSV_PRI 000000FF Symbol: NVIC_PENDSV_PRI Definitions At line 59 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 190 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: NVIC_PENDSV_PRI used once NVIC_SYSPRI14 E000ED22 Symbol: NVIC_SYSPRI14 Definitions At line 58 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 189 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: NVIC_SYSPRI14 used once 4 symbols ARM Macro Assembler Page 1 Alphabetic symbol ordering External symbols OSIntExit 00000000 Symbol: OSIntExit Definitions At line 36 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses None Comment: OSIntExit unused OSPrioCur 00000000 Symbol: OSPrioCur Definitions At line 32 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 297 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OSPrioCur used once OSPrioHighRdy 00000000 Symbol: OSPrioHighRdy Definitions At line 33 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 298 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OSPrioHighRdy used once OSRunning 00000000 Symbol: OSRunning Definitions At line 31 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 200 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OSRunning used once OSTCBCur 00000000 Symbol: OSTCBCur Definitions At line 34 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 95 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm At line 286 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 302 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm OSTCBHighRdy 00000000 Symbol: OSTCBHighRdy Definitions At line 35 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm ARM Macro Assembler Page 2 Alphabetic symbol ordering External symbols Uses At line 122 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm At line 303 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm OSTaskSwHook 00000000 Symbol: OSTaskSwHook Definitions At line 37 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 293 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OSTaskSwHook used once OS_CPU_ExceptStkBase 00000000 Symbol: OS_CPU_ExceptStkBase Definitions At line 38 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-Co rtex-M4\Generic\RealView\os_cpu_a.asm Uses At line 196 in file ..\..\Src\Micrium-DK-TM4C129X-OS2\uCOS-II\Ports\ARM-C ortex-M4\Generic\RealView\os_cpu_a.asm Comment: OS_CPU_ExceptStkBase used once 8 symbols 360 symbols in table